Xilinx Synthesis Technology - XST Components
Your VHDL/Verilog code gets synthesized into one of the following Xilinx FPGA components List of XST specific components Carry logic - MUXCY, XORCY, MULT_AND RAM - Block, Distributed Shift Register LUTs - SRL16, SRL32 Clock Buffers - IBUFG, BUFG, BUFGP, BUFR Multiplexers - MUXF5, MUXF6, MUXF7, MUXF8 Arithmetic Functions - DSP48, MULT18x18 - Courtesy of Xilinx ISE Help Topics
First 22nm FPGA →
Industry’s first 22 nm FPGA has come. No its not from Xilinx or Altera. Achronix has created 22 nm FPGA’s using Intel’s fab. They’ve challenged the BIG 2 of FPGA world. Achronix doesn’t even have a Wikipedia entry. Kudos to Achronix. Check the link for more details.
FPGA Distributed RAM
FPGA’s contain Block RAM (BRAM) & Distributed RAMs (DRAM). BRAM’s are dedicated memory blocks. Each FPGA has them. FPGA datasheets typically specify the Total BRAM in Kbits. DRAM’s are RAM’s that can be constructed using Look-Up-Tables (LUT). SRAM based FPGA’s have LUTs. These LUTs can be used as a small block of RAM by combining cells; called DRAMs. This...
XOR Gate is a 1-bit ADDER XNOR Gate is a 1-bit COMPARATOR.– Digital Design Tip
EDIF Netlist is always device independent– FPGA Tip
VHDL Tip : Use Integer Range Check
Integer has a range from -(2**31)-1 to (2**31)-1 but rarely do we use that range. I would recommend to always declare integer with a Range as shown below. Example Integer Declaration: The range 0 to 1E3 acts as a RANGE CHECK. It does NOT refer to the memory to be allocated for integer. If you exceed the range, simulator shows an error. I checked with ModelSim & it issues a fatal error.
DO-254 for FPGA Designer - White Paper by Xilinx... →
There’s finally a standard for FPGA designers to tackle Sigle Event Upsets & other problems. It is based on DO-178B which is a software standard. Title is DO-254 Design Assurance Guidance for Airborne Electronic Hardware & published by RTCA Inc. Here’s a link to a White Paper published by Xilinx
Notepad++ Compare Plugin
I came across this additional plugin for Notepad++ which is very efficient. Compares 2 files with highlighting & status flags. Can also compare to file on SVN base. Here’s a link to the plugin. Just add the *.dll file into the plugin directory of Notepad++ Here’s the link to NPP-Compare plugin http://sourceforge.net/projects/npp-compare/ I’ve written about Notepad++...
Summary of FPGA development boards →
This link provides a list of some entry-level FPGA boards. They all work with the free software from the FPGA vendors.
Terminal Client for Serial Communication
We often work with serial communication (RS232) which requires a COM port & a software application which can interpret UART protocol. Hyperterminal is one such application which can be used to read/write data from/to serial ports. Hyperterminal is available as a default application in Windows PC which can be located in Start -> Programs -> Accessories -> Communication ->...
Xilinx ISE Source Files List (click to open) →
The table shows the source file types that appear in the Project Navigator Sources tab.Available source types vary depending on your project properties (top-level module type, device type, synthesis tool, and language). The last column describes what to expect when creating the file with the New Source wizard and, if applicable, includes the tool launched when using the New Source wizard or when...
SVN for FPGA projects
For FPGA projects with many designers in a team it’s always better to have a sub-version control system. For software projects its pretty simple to add the source files like .c, .h etc. but FPGA designs typically have many input & output files. Here are the files I keep on SVN. I use Tortoise SVN with Xilinx ISE by keeping the following source...
"Hello World" equivalent on FPGA - Beginner...
Every programming book begins with “Hello World” as the first code. The hardware equivalent of “Hello World” would be “Glowing LED’s” Here’s what you’ll need 1. FPGA Board with User LED’s (duh) 2. USB programming cable or JTAG programmer 3. Design software by FPGA vendor Choose an HDL Language & simulator. I used VHDL with...
FPGA Clock Schemes →
This (click on Heading) is a brilliant article on FPGA Clocking by Tim Behne. Originally appeared in EETimes. Notes —> Skew is MAXIMUM delay from clk input of one FF to clk input of another FF Skew < Propagation Time between two FFs for clock to work properly FPGA’s have low skew resources. Use them.
FPGA Development Flow Output files & Reports
This block diagram shows output files/reports at each stage of FPGA Development. However, this chart is specific to Xilinx FPGA’s. (Image courtesy of Xilinx Inc)
The short term phase variation of the significant instants of a digital signal...– NIST definition of Jitter
FPGA Micro Kit
If you’re really keen on experimenting with FPGA’s its time you own one now. There are many micro-kits available in the market which are inexpensive, have good documentation, come with FPGA programming software’s, and don’t require JTAG programmers (they usually come with USB to JTAG converters). If you’re fortunate enough to work with kits provided by...
I’ve seen many sites with queries on VHDL Editors. I’ll list a few of them here. These are NOT IDE’s. Notepad++ with VHDL plugin - Works amazingly well on Windows. Its a very lightweight program. Pros : fullscreen option, code folding, good color schemes Cons: no in-built VHDL templates gVIM & Emacs if you swear by UNIX Sigasi HDT - Eclipse based environment ...
VHDL Free E-Book
Here’s the link for a free VHDL E-Book http://t.co/UEX9NMSJ I would also recommend to download the VHDL Quick Reference from Synthworks. Happy Coding :)
Prerequisites to FPGA Design
You’ll need fairly good know-how in Boolean Algebra Digital Circuits Hardware Description Language or HDL like VHDL/Verilog Coding in a programming language like C for rendering ideas into syntax and a lot of Patience.
There can’t be a blog about Programmable Logic without defining a logic gate right? I found this definition in a book I read about a year back & it stuck to my head. Gate is a circuit with multiple inputs and one output that is energized only when a designated set of input pulses is received. Image Courtesy of Deviantart.com user ~jsoaresgeral