FPGA DSP Slices
The concept of utilizing FPGAs for DSP operations is fairly well understood, established, and recognized within the signal processing industry. FPGA’s have DSP slices to implement signal processing functions. The DSP operation most commonly used is Multiply-Accumulate or MAC operation. A MAC block is also used as a building block for more complex DSP applications like filtering. FPGA DSP...
India VLSI Design Services Study 2012 →
You should read this if you’re working in VLSI or keen to join a VLSI design services firm. Click on Heading or this link.
FPGA Course for Beginners →
Click on the “Title” for a ‘free’ FPGA course. Yes there is awesome free stuff available on the internet. Kudos to the creators of the page.
Arithmetic Operations using Xilinx FPGA
We often use basic arithmetic operations for synthesis - adders, multipliers & sometimes the division operation. Some useful tips while using arithmetic operators: It is always recommended to use advanced options for synthesis in XST like “Use Mult”, “Use DSP” while using arithmetic operations. Check for customizable IP Cores. Most arithmetic operations are covered...
Fascinating Trivia on Decimation
The original meaning of “decimation” was that the Roman general killed one out of every ten centurions, as a way to instill order through fear. The same concept is used in the concept of Decimation used often in Signal Processing & VLSI terminologies. In signal processing decimation implies downsampling. In decimation we take 1 out of ‘N’ samples where N is the...
There are 4 timing paths we need to analyze in a sequential circuit Input-Clock path Clock-Clock path Clock-Output path Input-Output path For more updates on timing, watch this space.
Timing Hazards & Glitches
Timing hazards are fluctuations occurring during transient period i.e before output reaches steady state value. These fluctuations cause very short/narrow pulses called glitches. Circuit is said to have timing hazards if it has glitches. Timing hazards can be either static or dynamic. Dynamic hazards occur when the output produces a L->H or H->L transition. Multiple 1-bit changes...
Xilinx's Vivado Design Suite
It seems Xilinx has released a new Design Suite for FPGA & SoC designs. Is it an ISE replacement? They came out with a press release last week. Check this link : http://bit.ly/K1yMB2 Watch this space for more :)
FPGA File Management Tip
Tips to save disk space Xilinx ISE: Manual Copy of Sources While migrating from one design to another copy ONLY the source files like vhd, ucf, xco, cdc files (xco refers to Xilinx Coregen file & cdc is related to Chipscope pro). If there are filters don’t forget to move the .coe & .mif Other files can be ignored while manually copying as they are the generated files after...