**Introduction**

Most of you familiar with signal processing would’ve heard the term Hilbert Transform. We’ll call it HT from here on. There are other transform in DSP like Laplace, Fourier, Z etc which are more popular & used across multiple domains. Basically transform, as the word suggests is a mathematical process which converts one form of signal to another. Some are used only for purely analytic purposes (Fourier) while some are used for real-time signal processing like Hilbert.

HT ‘transforms’ the phase of the signal. It performs a phase shift of -90°. Yes you read it right, it is negative 90° phase shift. Generally, it is mentioned as a 90° phase shift without explicitly mentioning positive or negative shift. The reason is due to the concept of positive & negative frequencies. HT would phase shift positive frequency component by -90° while a negative frequency would be shifted by +90°.

**Where could we use HT?**

I’m sure there are multiple uses but the one I’m aware of is Quadrature processing. The term quadrature processing refers to dealing with In-phase, Quadrature-phase signals, i.e I,Q signals. I,Q signals are used for modulation & demodulation techniques. Quadrature modulation/demodulation offers many advantages over conventional approaches which can be discussed in another post.

For example, SSB demodulation by phasing method uses Hilbert transform to phase shift the incoming modulated signal to -90°.

**FPGA Implementation (Xilinx) **

Hilbert transformers can be easily implemented in Xilinx FPGA’s using FIR compiler IP. HT coefficients can be generated using Matlab FDA Tool. It is important to note that the Hilbert coefficient structure should contain alternate zeroes for FIR compiler to infer the filter as a Hilbert Structure.

Snapshot shows Hilbert Transformer using FDA Tool.

Generated Coefficients for Hilbert transformer

As you can see, every alternate coefficient is zero valued, which the FIR compiler infers as a Hilbert Filter structure.

FIR IP Core generates I, Q output (dout_i, dout_q in IP symbol) if the Hilbert structure is inferred properly. The output is -90° phase shifted. HT of cosine is sine and HT of sine is -cosine

* HT is predominantly used in quadrature Signal Processing. *

This post has deliberately come after a long gap as there are other blogs like the recently launched Programmable Planet which is far superior in content and substance.

Fast Fourier Transforms are almost ubiquitous for anyone dealing with signal processing & communications systems. Time domain analysis doesn’t provide us much required information as signal processing mostly relies on frequency domain techniques like modulation, up/downconversion, filtering. In short FFT is required in almost every design for either on-line or off-line analysis. For example, Peak search/scan is generally performed in spectral domain.

Xilinx Fast Fourier Transform IP Core provides 4 architectures. There is obviously a trade-off between speed (performance) & area.

I’ve considered an example of 64k (65536) transform length clocked at 100 MSPS & target data rate of 100 MSPS. Table shows the theoretical latency & resource estimates provided by Xilinx IP core.

From the table, the trade-off vis-a-vis FPGA Architectures is clear.

We know some computers use 64-bit words.

2^64 is approximately 1.8 x 10^18 - that’s a pretty large number.

So in fact if we started incrementing a 64-bit counter once per second at the beginning of the universe (20 billion yrs ago), the MSB’s of the counter would still be all zeroes.

*~ Excerpts from a book on Digital Signal Processing *

The concept of utilizing FPGAs for DSP operations is fairly well understood, established, and recognized within the signal processing industry.

FPGA’s have DSP slices to implement signal processing functions. The DSP operation most commonly used is Multiply-Accumulate or MAC operation. A MAC block is also used as a building block for more complex DSP applications like filtering.

**FPGA DSP slice** essentially **implements** a **MAC** operation.

Xilinx calls this slice “XtremeDSP DSP48”. (*probably because it handle a maximum **of 48-bit addition)*

*Image illustrates DSP48E used in Virtex-5 devices & its features (Courtesy of Xilinx Inc) *

There are 3 variants of DSP slices used in Xilinx FPGA’s- DSP48A, DSP48 & DSP48E.

(Image Courtesy of Xilinx Inc)

Xilinx has a good number of DSP elements in FPGA devices with** SX series**.

*For more info on Comparison of conventional DSP processing vis-a-vis FPGA-based DSP watch this space. *

The original meaning of “decimation” was that the Roman general killed one out of every ten centurions, as a way to instill order through fear.

The same concept is used in the concept of Decimation used often in Signal Processing & VLSI terminologies. In signal processing decimation implies downsampling. In decimation we take 1 out of ‘N’ samples where N is the decimation factor. For example if we have a 100 MHz sampled data decimated by a factor of 10, then we take 1 sample for every 10 clocks of 100 MHz so the output is 10 times slower at 10 MHz. It is also used while describing clock domains.