This post has deliberately come after a long gap as there are other blogs like the recently launched Programmable Planet which is far superior in content and substance.
Fast Fourier Transforms are almost ubiquitous for anyone dealing with signal processing & communications systems. Time domain analysis doesn’t provide us much required information as signal processing mostly relies on frequency domain techniques like modulation, up/downconversion, filtering. In short FFT is required in almost every design for either on-line or off-line analysis. For example, Peak search/scan is generally performed in spectral domain.
Xilinx Fast Fourier Transform IP Core provides 4 architectures. There is obviously a trade-off between speed (performance) & area.
I’ve considered an example of 64k (65536) transform length clocked at 100 MSPS & target data rate of 100 MSPS. Table shows the theoretical latency & resource estimates provided by Xilinx IP core.
From the table, the trade-off vis-a-vis FPGA Architectures is clear.
Configurable Logic Blocks (CLB) are programmable elements inside a Xilinx FPGA.
The figure shown below depicts FPGA Device fabric which is made up of several CLB’s (Snapshot taken from Xilinx PlanAhead Tool). Each of those boxes inscribed in blue are CLB’s which consists of slices & other components.
Virtex-5 CLB
A Virtex-5 CLB Tile consists of 2 SLICES. Figure depicts each CLB tile consisting of 2 slices. The components have been labelled for better understanding.
The above snapshot is taken from PlanAhead tool which is part of ISE Design Suite System Edition.
Each slice in a CLB consists of a 6 input LUT, Multiplexers (2:1), Carry logic made up of MUX & XOR gates, and D-Flip flops. All our logic gets mapped into these components using synthesis algorithms.
For more on FPGA architectures watch this space.
The concept of utilizing FPGAs for DSP operations is fairly well understood, established, and recognized within the signal processing industry.
FPGA’s have DSP slices to implement signal processing functions. The DSP operation most commonly used is Multiply-Accumulate or MAC operation. A MAC block is also used as a building block for more complex DSP applications like filtering.
FPGA DSP slice essentially implements a MAC operation.
Xilinx calls this slice “XtremeDSP DSP48”. (probably because it handle a maximum of 48-bit addition)
Image illustrates DSP48E used in Virtex-5 devices & its features (Courtesy of Xilinx Inc)
There are 3 variants of DSP slices used in Xilinx FPGA’s- DSP48A, DSP48 & DSP48E.
(Image Courtesy of Xilinx Inc)
Xilinx has a good number of DSP elements in FPGA devices with SX series.
For more info on Comparison of conventional DSP processing vis-a-vis FPGA-based DSP watch this space.
We often use basic arithmetic operations for synthesis - adders, multipliers & sometimes the division operation.
Some useful tips while using arithmetic operators:
- It is always recommended to use advanced options for synthesis in XST like “Use Mult”, “Use DSP” while using arithmetic operations.
- Check for customizable IP Cores. Most arithmetic operations are covered in FPGA vendor specific IP’s.
- However if you wish to use +,*,/ operators you will need to include libraries which define these operators.
Table shows VHDL Libraries needed to be added for specific arithmetic operations
It seems Xilinx has released a new Design Suite for FPGA & SoC designs. Is it an ISE replacement? They came out with a press release last week.
Check this link : http://bit.ly/K1yMB2
Watch this space for more :)
- While migrating from one design to another copy ONLY the source files like vhd, ucf, xco, cdc files (xco refers to Xilinx Coregen file & cdc is related to Chipscope pro). If there are filters don’t forget to move the .coe & .mif
- Other files can be ignored while manually copying as they are the generated files after synthesis, implementation etc of new design. This would save a lot of space instead of copying the whole project while integrating several modules.
- You could also use “Add copy of Source” from Xilinx ISE available in the ‘Design’ Tab.
- If you’re using ModelSim for simulation, there are chances that your project folder is very bulky.
- It is most likely due to the optimization folders created by modelsim, .dat files for test bench and wave viewer files (like wlf). You can ignore these files as they occupy a lot of disk space.
- This is all stored in the ‘WORK’ sub-folder under your project folder
- Just delete the ‘WORK’ folder after your simulation to save space.
Your VHDL/Verilog code gets synthesized into one of the following Xilinx FPGA components
List of XST specific components
- Carry logic - MUXCY, XORCY, MULT_AND
- RAM - Block, Distributed
- Shift Register LUTs - SRL16, SRL32
- Clock Buffers - IBUFG, BUFG, BUFGP, BUFR
- Multiplexers - MUXF5, MUXF6, MUXF7, MUXF8
- Arithmetic Functions - DSP48, MULT18x18
- Courtesy of Xilinx ISE Help Topics
