We know some computers use 64-bit words.
2^64 is approximately 1.8 x 10^18 - that’s a pretty large number.
So in fact if we started incrementing a 64-bit counter once per second at the beginning of the universe (20 billion yrs ago), the MSB’s of the counter would still be all zeroes.
~ Excerpts from a book on Digital Signal Processing
- Timing hazards are fluctuations occurring during transient period i.e before output reaches steady state value.
- These fluctuations cause very short/narrow pulses called glitches.
- Circuit is said to have timing hazards if it has glitches.
- Timing hazards can be either static or dynamic.
- Dynamic hazards occur when the output produces a L->H or H->L transition.
- Multiple 1-bit changes causes glitches because of different propagation delay of convergent paths.
Glitches in Multi-bit Counter
- If you observe the post-route simulation of a multi-bit counter you’re most likely to observe glitches where multiple 1-bit change occurs.
- For example if a counter is changing from “1111” to “0000” there is a 4-bit change which is susceptible to glitches.
- The solution is to reduce the number of 1-bit changes.
- It can be done by employing other methods of encoding for counter instead of a simple binary counter. Gray, one-hot, one-cold or any other counter with lesser number of bit change can overcome the problem.
- The same logic even applies to FSM encoding. It is better to use optimum state encoding to avoid glitches.
Some parts of this post are inspired from the great book on RTL design by Pong Chu published by Wiley IEEE Press.